Computer systems such as computer workstations operate due to the passage of information between at least one microprocessor and various subsystems. Communications between the microprocessor(s) and subsystems occur over a data communication pathway called a bus. In a present-day system, there are often multiple processors that are capable of "driving" a bus by requesting or sending data over the bus. In such a system, communications may be synchronized to a bus clock. In the resulting multi-drop system that supports synchronous bus communications, detection of faults can be difficult.
Since bi-directional buses by their very nature can be driven by multiple sources and are subject to various phenomena such as cross talk, reflections, etc., error isolation is difficult. Typically, these types of buses are protected by parity-checking or Error Correcting Code ("ECC") circuits. On a common bus, several receivers and even the driver of the bus may report an error at the same time. To improve the fault isolation, both the receiver that detected the error and the bus driver must be identified. This invention provides a method for locating the driver of a bus when errors occur on a multi-drop clocked synchronous I/O or system bus for fault isolation purposes.
One goal of fault-detection schemes in synchronous multi-drop systems is to identify the receiver and the driver of the communication in progress at the time a transmission error is detected. In current schemes, it is difficult to identify the bus driver at the time of error without complex investigation involving the arbiter of the system, checking the command on the bus, etc. The present method overcomes the complexity of prior art fault detection systems by latching the bus-driver-enable signal in a shift register to aid in detection of the bus driver at the time of error.